The present invention relates generally to integrated circuits, and more specifically, to integrated circuit interconnect structures.
Integrated circuits (ICs) are typically fabricated from one or more layers of different materials. Some layers, such as polysilicon layers, are used to form semiconductor devices, while other layers, such as patterned metal layers, provide electrical connections between semiconductor devices. Referring to FIG. 1, a conventional intermediate interconnect structure 100 is illustrated following deposition of an optical planarization layer (OPL) 102. The intermediate interconnect structure 100 includes one or more dielectric layers 104 configured to isolate one or more metal contacts such as, for example, source/drain (S/D) metal contacts 106 and gate metal contacts 108. The OPL 102 is typically used as a masking layer to form one or more local metal layers (M0) (not shown).
Local contact vias are typically formed in the dielectric layer 104 so as to establish contact between the metal contacts 106/108 and a respective local metal layer (M0). For example, a first set of trenches 110 are formed through the dielectric layer 104 in preparation for forming a first set of local contact vias (CA) intended to contact the S/D metal contacts 106. Similarly, a second set of trenches 112 are formed through the dielectric layer 104 in preparation for forming a second set of local contact vias (CB) intended to contact the gate metal contacts 108. When filling the trenches 110/112 with the OPL 102, however, a portion of the OPL's upper surface 114 located above the contact trenches 110/112 is formed non-planar with respect to the remaining upper surface 114 of the OPL 102 due to the depth of the contact trenches 110/112. As shown in FIG. 1, for example, a portion of the OPL upper surface located above the trenches 110/112 may become concaved thereby forming a crater region 116 in the OPL 102. Thus, the crater region 116 region may have a first height (H1) that is below a second height (H2) of the remaining OPL upper surface 114.
A photoresist layer 118 is typically deposited on the OPL upper surface 114 and patterned in preparation for forming the local metal layers (M0) (See FIG. 2). However, the crater regions 116 cause over-etched corners 120 in the M0 pattern 122. Following the removal of the OPL layer 102, the over-etched corners 120 cause the formation of eroded CA and/or CB contact trenches 124, i.e., contact trenches where the corners 126 are not ninety degrees (see FIG. 3). The eroded contact trenches 124 can lead to electrical shorting (i.e., short-circuit paths) between the subsequent local metal layer M0 (i.e., the metal layer formed after filling the M0 patterns) and any underlying contact levels.